Workshop Program

13:00 - 14:00 [Keynote] TBD
TBD [Link]
Abstract
Recording
14:00 - 14:30 Session 1: GPU Architecture Exploration
[Paper] Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems
Kazi Asifuzzaman (Oak Ridge National Laboratory), Narasinga Rao Miniskar(Oak Ridge National Laboratory), William Godoy(Oak Ridge National Laboratory), Oscar Hernandez (Oak Ridge National Laboratory) and Jeffrey Vetter(Oak Ridge National Laboratory)
Abstract
Recording
[Paper] Exploring the Wafer-Scale GPUs.
Daoxuan Xu (William & Mary), Le Xu (Byte Dance Inc.), Jie Ren (William & Mary) and Yifan Sun (William & Mary)
Abstract
Recording
14:30 - 15:00 Session 2: GPU Characterization and Modeling
[Paper] Modeling Utilization to Identify Shared-memory Atomic Bottlenecks.
Rongcui Dong (University of Rochester) and Sreepathi Pai (University of Rochester)
Abstract
Recording
[Paper] Uncovering Detailed Power Characterizations of GPUs on Edge Platforms
Mujahid Al Rafi (UC Merced), Kevin Chau (UC Merced) and Hyeran Jeon (UC Merced)
Abstract
Recording
15:00 - 15:30 Coffee Break
15:30 - 16:00 Session 3: Tensor Cores and Memory Accelerators
[Paper] Can Tensor Cores Benefit Memory-Bound Kernels?
Lingqi Zhang (RIKEN Center for Computational Science), Jiajun Huang (UC Riverside) and Mohamed Wahib (RIKEN Center for Computational Science)
Abstract
Recording
[Paper] ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs.
Nicolás Meseguer (Universidad de Murcia), Yifan Sun (William & Mary), Michael Pellauer (NVIDIA), José L. Abellán (Universidad de Murcia) and Manuel E. Acacio (Universidad de Murcia)
Abstract
Recording
16:00 - 16:45 Session 4: GPU Applications and Algorithm Optimization
[Paper] Efficient Parallel Implementation of Non-Local Means Algorithm on GPU.
Xiang Li (Nanjing University), Qiong Chang (Institute of Science Tokyo), Yun Li (Nanjing University) and Jun Miyazaki (Institute of Science Tokyo)
Abstract
Recording
[Paper] Evaluating Parallel Sliding Window Techniques: Algorithmic and Multi-GPU Advancements with Fast-PII.
Seth Ockerman (University of Wisconsin Madison) and Erin Carrier (Grand Valley State University)
Abstract
Recording
[Paper] Optimizing Auto-tuning of OpenMP Offload kernels for performance and power.
Nafis Mustakin (UC Riverside) and Daniel Wong (UC Riverside)
Abstract
Recording
TBD

Important Dates (Tentative) (11:59 pm, Anywhere on Earth)

  • Papers due: December 2 December 16, 2024
  • Notification: January 20, 2025
  • Final paper due: February 17, 2025

Submission Guidelines

Full paper submissions must be in PDF format for A4 or US letter-size paper. They must not exceed 6 pages (excluding references) in standard ACM two-column sigplan format (review mode, sigplan template). Authors can select if they want to reveal their identity in the submission. Word and LaTeX atTemplates for ACM format are available for Microsoft Word, and LaTeX at: https://www.acm.org/publications/proceedings-template

Submission Site: GPGPU 2025

Workshop Organizers

Hyeran Jeon Yifan Sun Daniel Wong
Co-chair Co-chair Co-chair
UC Merced William & Mary UC Riverside
Hyeran Jeon is an Associate Professor in the Department of Computer Science and Engineering at the University of California, Merced. She received her PhD at the University of Southern California. Her research interests lie in energy-efficient, reliable, and secure GPU architectures. She received NSF CAREER award in 2024. Yifan Sun is an Assistant Professor in the Department of Computer Science at William & Mary since Fall 2020. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at Northeastern University in 2020. His research interests lie in GPU architecture, performance evaluation, and performance modeling. Daniel Wong is an Associate Professor in the Department of Electrical and Computer Engineering at the University of California, Riverside. He received his PhD in Electrical Engineering at the University of Southern California (USC). His research spans GPU Architecture, High Performance Computing, and Warehouse-scale Computing. His current research focuses on energy efficient and high performance computing systems from datacenter scale to micro-architectures. His research work has been recognized with an IEEE MICRO Top Picks in 2012 and an NSF CAREER award in 2020.
Nafis Mustakin Yuan Feng
Publication Chair Web Chair
UC Riverside UC Merced
Please contact the organizers if you have any questions.

Program Committee

  • Dongho Ha (MangoBoost Inc.)
  • Hongyuan Liu (The Hong Kong University of Science and Technology)
  • Seonjin Na (Georgia Institute of Technology)
  • Harisankar Sadasivan (AMD)
  • Devashree Tripathy (IIT Bhubaneswar)
  • Jinyang Liu (University of Houston)
  • Yujia Zhai (NVIDIA)
  • Jie Ren (William & Mary)

History and Impact

David Kaeli (Northeastern) and John Cavazos (Delaware) started this GPGPU workshop series, which was first held in 2007 at Northeastern University. In 2008, the workshop was held with ASPLOS 2008. This trend continued and this GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 to 2018, the GPGPU workshop was co-located with PPoPP. In 2019 and 2020, the GPGPU workshop is co-hosted by Adwait Jog (William & Mary), Onur Kayiran (AMD), and Ashutosh Pattnaik (ARM). The average citation count (as per Google Scholar), for a GPGPU workshop paper is currently 37.5, where there have been 8 influential papers with 100+ citations.

Previous versions of the GPGPU workshop: