Important Dates

  • Papers due: Dec 12, 2023

Submission Guidelines

Full paper submissions must be in PDF format for A4 or US letter-size paper. They must not exceed 6 pages (excluding references) in standard ACM two-column sigplan format (review mode, sigplan template). Authors can select if they want to reveal their identity in the submission. Word and LaTeX atTemplates for ACM format are available for Microsoft Word, and LaTeX at:

Submission Site: GPGPU 2024

Workshop Organizers

José Cano Reyes Hyeran Jeon Yifan Sun Daniel Wong
Co-chair Co-chair Co-chair Co-chair
University of Glasgow UC Merced William & Mary UC Riverside
José Cano Reyes is a Senior Lecturer (Associate Professor) in the School of Computing Science at the University of Glasgow, where José Cano Reyes leads the Glasgow Intelligent Computing Laboratory (gicLAB) and José Cano Reyes is the deputy Lead of the GLAsgow Systems Section (GLASS). José Cano Reyes is also a visiting member of ICSA in the School of Informatics at The University of Edinburgh. Hyeran Jeon is an Assistant Professor in the Department of Computer Science and Engineering at the University of California, Merced. She received her PhD at the University of Southern California. Her research interests lie in energy-efficient, reliable, and secure GPU architectures. Yifan Sun is an Assistant Professor in the Department of Computer Science at William & Mary since Fall 2020. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at Northeastern University in 2020. His research interests lie in GPU architecture, performance evaluation, and performance modeling. Daniel Wong is an Associate Professor in the Department of Electrical and Computer Engineering at the University of California, Riverside. He received his PhD in Electrical Engineering at the University of Southern California (USC). His research spans GPU Architecture, High Performance Computing, and Warehouse-scale Computing. His current research focuses on energy efficient and high performance computing systems from datacenter scale to micro-architectures. His research work has been recognized with an IEEE MICRO Top Picks in 2012 and an NSF CAREER award in 2020.
Nafis Mustakin Yuan Feng
Publication Chair Web Chair
UC Riverside UC Merced
Please contact the organizers if you have any questions.

Program Committee

  • Kishore Punniyamurthy (AMD Research)
  • Hongyuan Liu (The Hong Kong University of Science and Technology (Guangzhou))
  • Ian Colbert (AMD)
  • Bastian Hagedorn (NVIDIA)
  • Mehmet Belviranli (Colorado School of Mines)
  • Jie Ren ( William & Mary)
  • Jieyang Chen (UC Riverside)
  • Yunho Oh (Korea University)
  • Hoda Naghibijouybari (Binghampton University)
  • Johannes Doerfert(Lawrence Livermore National Laboratory)

History and Impact

David Kaeli (Northeastern) and John Cavazos (Delaware) started this GPGPU workshop series, which was first held in 2007 at Northeastern University. In 2008, the workshop was held with ASPLOS 2008. This trend continued and this GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 to 2018, the GPGPU workshop was co-located with PPoPP. In 2019 and 2020, the GPGPU workshop is co-hosted by Adwait Jog (William & Mary), Onur Kayiran (AMD), and Ashutosh Pattnaik (ARM). The average citation count (as per Google Scholar), for a GPGPU workshop paper is currently 37.5, where there have been 8 influential papers with 100+ citations.

Previous versions of the GPGPU workshop: