GPGPU 2024

The 16th Workshop on General Purpose Processing Using GPU (GPGPU 2024)

March 2, 2024, Edinburgh, UK

Zoom Link: https://ucmerced.zoom.us/j/86811329531?pwd=Ym5zQTRHSjdZTnpua1RKb2FSMGU3UT09

GPUs are delivering more and more computing power required by modern society. With the growing popularity of massively parallel devices, users demand better performance, programmability, reliability, and security. The goal of this workshop is to provide a forum to discuss massively parallel applications, environments, platforms, and architectures, as well as infrastructures that facilitate related research.
Authors are invited to submit papers of original research in the general area of GPU computing and architectures. Topics include, but are not limited to

GPU Architecture and Hardwares

Next-generation GPU architectures
Energy-efficient GPU designs
Scalable multi-GPU systems
GPU memory hierarchies and management

Programming Models and Compilers

High-level programming abstractions for GPUs
Compiler optimizations for GPU codes
Source-to-source translations and tools
Debugging and profiling tools for GPUs

GPU Algorithms and Data Structures

Parallel algorithms tailored for GPUs
Data structures optimized for GPU memory hierarchies
Algorithmic primitives and building blocks

Performance Optimization Techniques

Performance modeling and benchmarking
Auto-tuning and performance portability
Techniques for reducing communication overheads

GPU Applications

Case studies of real-world GPU applications
GPU applications in scientific computing, machine learning, graphics, and emerging field (e.g., quantum, neuromorphic, bioinformatics and genomics)
Performance comparisons between GPU and other parallel computing platforms

Integration of GPUs with Other Technologies

GPU and FPGA co-processing
Hybrid systems (e.g., CPU-GPU, GPU-TPU integration)
Cloud-based GPU computing

Challenges and Future Trends

Reliability and fault tolerance in GPU systems
Security and privacy concerns in GPU computing
The future of heterogeneity in computing platforms
GPU programming and architecture education

Workshop Program

1:40 PM - 1:50 PM	Opening Remarks ▶ Recording
1:50 PM - 2:40 PM	[Keynote] Title: Open source GPU Hardware and Software Hyesoon Kim (Georgia Institute of Technology) [Link] ▶ Abstract Abstract: Graphics processors or data parallel architectures have become critical computing platforms for today’s workloads, heavily utilized in high-performance computing simulations and the recent explosion of training for large language model (LLM) AI models. Inspired by the open-source hardware community based on the RISC-V ISA, we have been developing a OpenGPU by extending RISC-V ISAs. The OpenGPU aims to provide a full stack of solutions for GPUs, capable of running OpenCL/CUDA workloads as well as 3D graphics pipelines. Additionally, we have developed Cupbop, which enables running CUDA on a broad range of parallel processors including X86, ARM, RISC-V, RISC-V GPU, and AMD GPUs. I will also discuss the future plans for Vortex and Cupbop. ▶ Recording

Session 1
2:40 PM - 3:00 PM	[Paper] Cache Cohort GPU Scheduling Vinay Ramakrishnaiah, Bradford Beckmann, William Ehrett, Rene Van Oostrum and Keith Lowery (AMD) ▶ Abstract With the ever-improving computation capability of GPUs, there is an increasing demand for higher memory bandwidth to supply the GPU cores with data. One way to improve effective memory bandwidth is with larger caches, and we have seen GPU vendors recently invest in very large last-level caches (LLCs). The key challenge is to maximize cache utilization and keep the active working set on-chip during the lifetime of a kernel. Software tiling optimizations can help, but programmers alone cannot anticipate dynamic cache capacity contention. To this end, we introduce the concept of cache cohorts: groups of kernels that share the same working set and thus can be efficiently scheduled together. Our approach uses the GPU command processor (CP) to track the occupancy of the LLC and throttles scheduling of the next cohort if there is no room. To evaluate the design space, we modify the existing GPU firmware on the AMD RX 7600 and RX 7900 XTX GPUs to prototype the scheduling scheme using real hardware. Our preliminary results show up to 27% reduction in execution time using the cache optimized scheduling technique on RX 7900 XTX. ▶ Recording
3:00 PM - 3:20 PM	[Paper] GPU-acceleration of neighborhood-based dimensionality reduction algorithm EmbedSOM Adam Šmelko, Martin Kruliš and Jiří Klepl (Charles University Prague, Czechia) ▶ Abstract Dimensionality reduction methods have found vast applications as visualization tools in diverse areas of science. Although many different methods exist, their performance is often insufficient for providing quick insight into many contemporary datasets. In this paper, we propose a highly optimized GPU implementation of EmbedSOM, a dimensionality reduction algorithm based on self-organizing maps. We detail the optimizations of kNN search and 2D projection kernels which comprise the core of the algorithm. To tackle the thread divergence and low arithmetic intensity, we use a modified bitonic sort for kNN search and a projection kernel that utilizes vector loads and register caches. The evaluated performance benchmarks indicate that the optimized EmbedSOM implementation is capable of projecting over 30 million individual data points per second. ▶ Recording
3:20 PM - 3:40 PM	[Paper] Regular Expressions on Modern GPGPUs Cheng Li and Clark Verbrugge (McGill University) ▶ Abstract Using GPUs is an effective way to accelerate regular expression (RE) matching, offering orders of magnitude faster processing than pure CPU approaches. Prior GPU-based RE acceleration methods, however, were developed on older GPU models and primarily aimed at expediting network packet inspection problems. In this work we conduct an updated study aiming to improve performance and enhance generality. We first incorporate prefiltering, verifying whether simpler parts of the RE can match before testing more complex RE components. We also observed that naive implementation of current designs on a modern GPU results in low thread occupancy, limiting performance, and improving the selection of GPU parameters is also crucial to optimizing performance. In combination our optimized design allows us to achieve 40x performance improvement over iNFAnt and up to 1900x faster than ASyncAP. Such an updated approach allows for faster, more general RE matching on modern GPUs. ▶ Recording
3:40 PM - 4:00 PM	Break

Session 2
4:00 PM - 4:20 PM	[Paper] Accelerating Stencil Computations on a GPU by Combining Using Tensor cores and Temporal Blocking Futa Kambe and Toshio Endo (Tokyo Institute of Technology) ▶ Abstract Stencil computations, which approximate differential equations in simulations, are important computations in highperformance computing. One of speed-up techniques is called temporal blocking, which reduces memory access by advancing computations of several time steps locally at a time. In addition, recent GPUs are equipped with units such as Tensor cores that specialize in matrix operations, and there is a research project TCStencil[1], which applies them to stencil computations. In this paper, we integrate these two techniques to accelerate computation speed of stencil computations even further. This integration is not trivial, however, since temporal blocking introduces wider halo regions, while Tensor cores only accelerate computations with restricted tensor sizes, such as 16×16. We describe our proposed method to alleviate performance issues. The evaluation results show that our implementations achieve notably speedup compared to existing versions. Especially, even compared to a version with Tensor cores, our implementation with deeper temporal blocking shows speedup of approximately 1.25 times. ▶ Recording
4:20 PM - 4:40 PM	[Paper] Exploring Page-based RDMA for Irregular GPU Workloads. A case study on NVMe-backed GNN Execution Benjamin Wagley (Colorado School of Mines), Pak Markthub (NVIDIA), James Crea, Bo Wu and Mehmet Belviranli (Colorado School of Mines) ▶ Abstract Paged memory systems for GPUs like NVIDIA's Unified Virtual Memory, offer a simple method for programmers to create out-of-core programs on GPUs. In the case of storage backed approaches, these systems can even handle larger than host memory systems as NVMe is used to back GPU memory through RDMA. However, paged memory systems can struggle with irregular access patterns. In this work, we analyze the limitations of paged, RDMA-backed GPU memory for out-of-core, irregular workloads, through a case study of GNN training. We highlight the key limitations of these systems that must be overcome before the true potential of RDMA backed GPU memory can be realized in a paged memory architecture. ▶ Recording
4:40 PM - 5:30 PM	[Panel] Panelists: Bradford Beckmann - AMD John Kim - KAIST Dong Li - UC Merced Daniel Wong - UC Riverside Yifan Sun - William & Mary Moderator: Seonjin Na - Georgia Institute of Technology ▶ Recording
5:30 PM - 5:40 PM	Closing Remarks ▶ Recording

Speaker: Hyesoon Kim (Georgia Institute of Technology)
Title: Open source GPU Hardware and Software

Abstract: Graphics processors or data parallel architectures have become critical computing platforms for today’s workloads, heavily utilized in high-performance computing simulations and the recent explosion of training for large language model (LLM) AI models. Inspired by the open-source hardware community based on the RISC-V ISA, we have been developing a OpenGPU by extending RISC-V ISAs. The OpenGPU aims to provide a full stack of solutions for GPUs, capable of running OpenCL/CUDA workloads as well as 3D graphics pipelines. Additionally, we have developed Cupbop, which enables running CUDA on a broad range of parallel processors including X86, ARM, RISC-V, RISC-V GPU, and AMD GPUs. I will also discuss the future plans for Vortex and Cupbop.

Bio: Hyesoon Kim is a professor in the School of Computer Science at the Georgia Institute of Technology and a co-director of the Center for Novel Computing Hierarchy. Her research areas include the intersection of computer architectures and compilers, with an emphasis on heterogeneous architectures such as GPUs and near-data processing. She is a recipient of the NSF Career Award and is a member of the MICRO/HPCA Hall of Fame. She is the chair of IEEE TCuARCH and an associate editor of Transactions on Architecture and Code Optimization. She is also an IEEE fellow.

Moderator: Seonjin Na (Georgia Institute of Technology)

Bio: Seonjin Na is a postdoctoral researcher in the School of Computer Science at Georgia Institute of Technology. Prior to joining Georgia Institute of Technology, he received his Ph.D. in School of Computing from Korea Advanced Institute of Technology in 2023. During his Ph. D studies, he has been working on designing secure architecture for accelerators such as GPUs, and NPUs and improving deep learning training performance. His research interests include GPU architecture, security, systems for machine learning, and accelerating large language models.

Speaker: John Kim (KAIST)

Bio: John Kim is currently a full professor in the School of Electrical Engineering at KAIST (Korea Advanced Institute of Science and Technology) in Daejeon, Korea. John Kim received his Ph.D. from Stanford University and B.S/M.Eng from Cornell University. His research interests include computer architecture, interconnection networks, security, and mobile systems. He has received a Google Faculty Research Award, Microsoft-Asia New Faculty Fellowship, and is listed in the Hall of Fame for ISCA, MICRO, and HPCA. He has also worked on the design of several microprocessors at Intel and at Motorola.

Speaker: Dong Li (UC Merced)

Dong Li is an associate professor at EECS, University of California, Merced. Previously, he was a research scientist at the Oak Ridge National Laboratory (ORNL). Dong earned his PhD in computer science from Virginia Tech. His research focuses on high performance computing (HPC), and maintains a strong relevance to computer systems. The core theme of his research is to study how to enable scalable and efficient execution of enterprise and scientific applications (including large-scale AI models) on increasingly complex parallel systems. Dong received an ORNL/CSMD Distinguished Contributor Award in 2013, a CAREER Award from the National Science Foundation in 2016, a Berkeley Lab University Faculty Fellowship in 2016, a Facebook research award in 2021, and an Oracle research award in 2022. His paper in SC'14 was nominated as the best student paper. His paper in ASPLOS'21 won the distinguished artifact award. He was also the lead PI for the NVIDIA CUDA Research Center at UC Merced. He is an associate editor for IEEE Transactions on Parallel and Distributed Systems (TPDS).

Speaker: Brad Beckmann(AMD)

Brad Beckmann is a Fellow at AMD Research and Advanced Development and works in Bellevue, WA. Currently, Brad is the Principal Investigator for a team of researchers pursuing a wide variety of endeavors that include CPU computation enhancements, advanced intelligent memory systems, and distributed GPU computing. Brad has worked at AMD since 2007 and has led projects innovating in GPU memory consistency models, GPU cache coherence, and on-chip networks. Prior to joining AMD, Brad worked as a software developer for Microsoft’s Windows Server Performance team. Brad completed his PhD degree in the Department of Computer Science at the University of Wisconsin-Madison where his doctoral research focused on physical and logical solutions to wire delay in large multi-core CPUs.

Important Dates

Papers due: Dec 12, 2023
Notification: Jan 25, 2024
Final paper due: Feb 17, 2024

Submission Guidelines

Full paper submissions must be in PDF format for A4 or US letter-size paper. They must not exceed 6 pages (excluding references) in standard ACM two-column sigplan format (review mode, sigplan template). Authors can select if they want to reveal their identity in the submission. Word and LaTeX atTemplates for ACM format are available for Microsoft Word, and LaTeX at: https://www.acm.org/publications/proceedings-template

Submission Site: GPGPU 2024

Workshop Organizers


José Cano	Hyeran Jeon	Yifan Sun	Daniel Wong
Co-chair	Co-chair	Co-chair	Co-chair
University of Glasgow	UC Merced	William & Mary	UC Riverside
José Cano is an Associate Professor in the School of Computer Science at the University of Glasgow, where he heads the Glasgow Intelligent Computing Laboratory (gicLAB) and is also Deputy Lead of the Systems Research Section. His research interests are in the broad areas of Computer Architecture, Computer Systems, Compilers, Machine Learning and Security. He is a senior member of IEEE and ACM.	Hyeran Jeon is an Assistant Professor in the Department of Computer Science and Engineering at the University of California, Merced. She received her PhD at the University of Southern California. Her research interests lie in energy-efficient, reliable, and secure GPU architectures. She received NSF CAREER award in 2024.	Yifan Sun is an Assistant Professor in the Department of Computer Science at William & Mary since Fall 2020. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at Northeastern University in 2020. His research interests lie in GPU architecture, performance evaluation, and performance modeling.	Daniel Wong is an Associate Professor in the Department of Electrical and Computer Engineering at the University of California, Riverside. He received his PhD in Electrical Engineering at the University of Southern California (USC). His research spans GPU Architecture, High Performance Computing, and Warehouse-scale Computing. His current research focuses on energy efficient and high performance computing systems from datacenter scale to micro-architectures. His research work has been recognized with an IEEE MICRO Top Picks in 2012 and an NSF CAREER award in 2020.


Nafis Mustakin	Yuan Feng
Publication Chair	Web Chair
UC Riverside	UC Merced

Please contact the organizers if you have any questions.

Program Committee

Kishore Punniyamurthy (AMD Research)
Hongyuan Liu (The Hong Kong University of Science and Technology (Guangzhou))
Ian Colbert (AMD)
Bastian Hagedorn (NVIDIA)
Yuhui Bao (Northeastern University)
Mehmet Belviranli (Colorado School of Mines)
Jie Ren ( William & Mary)
Jieyang Chen (UC Riverside)
Yunho Oh (Korea University)
Hoda Naghibijouybari (Binghampton University)
Johannes Doerfert(Lawrence Livermore National Laboratory)

History and Impact

David Kaeli (Northeastern) and John Cavazos (Delaware) started this GPGPU workshop series, which was first held in 2007 at Northeastern University. In 2008, the workshop was held with ASPLOS 2008. This trend continued and this GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 to 2018, the GPGPU workshop was co-located with PPoPP. In 2019 and 2020, the GPGPU workshop is co-hosted by Adwait Jog (William & Mary), Onur Kayiran (AMD), and Ashutosh Pattnaik (ARM). The average citation count (as per Google Scholar), for a GPGPU workshop paper is currently 37.5, where there have been 8 influential papers with 100+ citations.

Previous versions of the GPGPU workshop: